Modern Bare Metal Systems with Rust

A student-run short course on systems programming for modern, disaggregated embedded architectures. We bridge the gap between traditional microcontroller firmware and server-class driver development using the Raspberry Pi 5.

Instructor: Devansh Lodha

Term: TBD

Location: TBD

Time: TBD

Course Overview

This is a specialized short course designed for students interested in advanced systems programming. Unlike traditional embedded courses that focus on simple microcontrollers with flat memory maps, this course tackles the complexity of modern Single Board Computers (SBCs) like the Raspberry Pi 5, which utilize server-class disaggregated architectures.

Over five intensive sessions, we will demystify how to bring up a bare-metal kernel in Rust, covering the entire vertical stack from the instruction set up to the peripheral driver.

Learning Outcomes

By the end of this short course, you will understand:

  • PCIe Orchestration: How to manually manage the link between an Application Processor (BCM2712) and an I/O Southbridge (RP1).
  • Address Translation: How to configure Base Address Registers (BARs) and MMU windows.
  • Interrupt Routing: How Message Signaled Interrupts (MSI-X) work and how to configure the GICv2.
  • Hardware Debugging: How to reverse-engineer undocumented behavior in commodity silicon.

Prerequisites

  • Systems Programming: Comfort with C, C++, or Rust (pointers, memory management, bitwise operations).
  • Computer Architecture: Basic understanding of registers, interrupts, stacks, and virtual memory.
  • Hardware: A Raspberry Pi 5 and a USB-to-UART debug probe are highly recommended for following along.

Resources

  • Primary Reference: Bare Metal Orchestration on the Raspberry Pi 5 (Course Notes).
  • Datasheets:
    • RP1 Peripherals Specification
  • Language: The Rust Programming Language

Schedule

Week Date Topic Materials
1 TBD The Disaggregated Shift & Bootstrapping

Introduction to the BCM2712 and RP1 Southbridge. Setting up the Rust toolchain and transitioning from Assembly _start to Rust main at EL1.
2 TBD PCIe Root Complex & Address Translation

Initializing the PCIe Gen2 link. Configuring Inbound/Outbound windows (BARs) so the CPU can “see” the peripheral bus.
3 TBD RP1 Enumeration

Scanning the PCIe bus to discover the RP1 (Vendor ID 0x1DE4). Enabling Bus Mastering and mapping the Southbridge’s internal address space.
4 TBD Modern Interrupts (MSI-X & MIP)

Moving beyond physical IRQ wires. Configuring the Machine Interrupt Peripheral (MIP) “doorbell” and routing MSI-X messages to the CPU.
5 TBD Drivers & The Firmware Trap

Implementing the PL011 UART driver over PCIe. Debugging the critical VPU firmware conflict INT_MASKL_VPU to enable console output.